1. Field of the Invention
Embodiments of the present invention generally relate to methods for barrier layer, ruthenium layer and tungsten layer formation and, more particularly to ruthenium deposition processes for use in tungsten integration.
2. Description of the Related Art
Sub-quarter micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology possess high aspect ratio features, including contacts, vias, lines, or other apertures. Reliable formation of these features is very important to the success of VLSI and to the continued effort to increase quality and circuit density on individual substrates. Therefore, there is a great amount of ongoing effort being directed to the formation of void-free features having high aspect ratios of 10:1 (height:width) or greater.
Tungsten, replacing copper and aluminum, has recently become a choice metal for filling VLSI features, such as sub-micron high aspect ratio, interconnect features. However, tungsten has a propensity to disjoin from dielectric materials, such as polysilicon, silicon germanium and silicon oxides. The disjoining may minimally cause an increase in the contact resistance of the circuit if not cause complete failure of the electronic device. Adhesion layers or barrier layers are, therefore, deposited prior to tungsten metallization to prevent or impede the disjoining of the tungsten material on the substrate surface.
A typical sequence for forming an interconnect includes depositing one or more non-conductive layers, etching at least one of the layer(s) to form one or more features therein, depositing a barrier layer in the feature(s) and depositing one or more conductive layers, such as tungsten, to fill the feature. The barrier layer typically includes a refractory metal nitride and/or silicide, such as titanium or tantalum. Of this group, tantalum nitride is one of the most desirable materials for use as an adhesion/barrier layer because it has one of the lowest resistivities of the metal nitrides and makes a strong adhesion layer for tungsten metallization. A metal nitride layer, such as tantalum nitride, is typically deposited using conventional deposition techniques, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).
Conventional deposition processes have difficulty forming interconnect structures because these processes have problems filling sub-micron structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Often, the barrier layer bridges the opening of a narrow feature, resulting in the formation of one or more voids or discontinuities within the feature. Since voids increase the resistance and reduce the electromigration resistance of the feature, features having voids make poor and unreliable electrical contacts. Some processes have been developed to deposit barrier layers by atomic layer deposition (ALD), but tantalum nitride layers deposited by ALD are not commonly found in electronic devices. The lack of commercialization of tantalum nitride deposition by ALD is probably due to the additional cost of hardware and integration of the chamber into existing process platforms.
Alternatively, a thin film of a noble metal such as, ruthenium, palladium, platinum, cobalt, nickel and rhodium, among others may be used as a barrier layer or an underlayer for the metal-filled vias and lines. Usually these noble metal underlayers are deposited as barrier layers on dielectric materials for copper seed. However, ALD processes to deposit noble metals remain scarce in the art relative to transition metal ALD processes, such as to deposit titanium, tungsten or tantalum.
Therefore, a need exists, for a method to deposit an adhesion/barrier layer and tungsten in high aspect ratio interconnect features having good step coverage, strong adhesion and low electrical resistivity.